Programmable devices such as erasable programmable read only memories (EPROMs), flash memories, field programmable gate arrays (FPGA), programmable logic devices (PLD) and complex programmable logic devices (CPLD) often use programmable cells to store logic configurations. For example, PLDs and/or CPLDs may use erasable programmable read only memory (EPROM) cells to configure logic cells within the device. Alternatively, electrically erasable programmable read only memory (EEPROM) or flash memory cells may be used for these purposes. In general, these programmable cells have electrically isolated gates (floating gates) which may be used to store information in the form of charge, even in the absence of an operating voltage. In this way, a memory cell may be programmed, or not, to store a desired logic state.
Verifying the margin voltage of a programmable cell becomes important for such programmable devices. Margin voltages help determine the life and the reliability of a cell and, in addition, can determine the maximum operating voltage (Vcc) that a part (e.g., a PLD, CPLD or an FPGA) containing the cell can be operated at. During normal operation, a voltage is applied to the gate of a selected cell, usually Vcc (e.g., 0-4V). During margin mode or verify mode, a verify voltage is applied to the gate of the cell to determine if the cell retains its memory state. By checking a programmed cell above the normal operating voltage, one can guarantee that it will function under worst case conditions for the life of the device. FIG. 1 illustrates a prior scheme used to determine margins voltages for such programmable cells. Generally, a programmable cell 10 is provided with a verify voltage which may be produced by a voltage divider network 12. The verify voltage will be some fraction of a reference voltage Vpp 14. Selected fractions of the reference voltage can be applied through voltage divider network 12 to programmable cell 10 and the state of programmable cell 10 determined using a conventional sense amplifier 16.
In general, such a scheme provided for only three, hard-wired voltage levels to be applied as verify voltages. For example, a high voltage (e.g., 6.8V), corresponding to a significant fraction of the reference voltage, a low voltage (e.g., 3.5V), corresponding to a relatively small fraction of the reference voltage and a nominal voltage (e.g., 6.5V), corresponding to some intermediate fraction of the reference voltage between the high and low voltages. The high voltage (.sup.V verify-high) is used to check each cell as each cell is being programmed. The nominal voltage (.sup.V verify-nom) is used to check all of the cells after the part has been programmed and is the minimum voltage necessary to guarantee a reliably programmed cell. The low voltage (.sup.V verify-low) is used to check the erased cells. Thus, the scheme is relatively inflexible and provides a minimal amount of information. In addition, new silicon masks are required to produce different verify voltages.
Another important parameter for programmable devices is the voltage at which programmable cells within the device are to be programmed. In general, programmable cells are programmed by applying a programming voltage to the drain of the programmable cell through a load line circuit as shown in FIG. 2. Load line circuit 20 provides programmable cell 22 with a programming voltage from a voltage source 24. This programming voltage must be within a certain window of voltages across various process corners and voltage source conditions. To provide this voltage, a reference voltage circuit 26 may apply some fraction of the voltage 24 to load line circuit 20 for programming the programmable cell 22. However, because the load line circuit is inflexible, any changes in process parameters (e.g., as may be encountered when migrating to new process technologies) required a new silicon mask to produce a different optimum reference voltage circuit.